1. Field of the Invention
The present invention relates to a method and a device for driving a plasma display panel (PDP).
Increasing number of pixels in a PDP due to a large screen or a high definition cause increase of power consumption. It is necessary to reduce the power consumption for reducing load of a driving device and for taking measures against heat.
2. Description of the Prior Art
As a color display device, a surface discharge AC type PDP is commercialized. The surface discharge type has electrodes (display electrodes X and display electrodes Y) to be anodes and cathodes in display discharge for ensuring luminance. The display electrodes X and Y are arranged on a front substrate or a back substrate in parallel, and address electrodes (third electrodes) are arranged so as to cross the display electrode pairs. There are two forms of display electrode arrangement. In one form, a pair of display electrodes is arranged for each row of a matrix display. In another form, display electrodes X and display electrodes Y are arranged alternately at a constant pitch. In the latter form, each of the display electrodes except both ends of the arrangement works for displays of two neighboring rows. Regardless of the arrangement form, the display electrode pairs are covered with a dielectric layer.
In a surface discharge type PDP display, one of the display electrodes (pair) assigned to each row is used as a scan electrode for row selection, so as to generate address discharge between the scan electrode and the address electrode, and address discharge between the display electrodes triggered by the address discharge between the scan electrode and the address electrode. In this way, addressing is performed for controlling electrification quantity (wall charge quantity) of the dielectric layer in accordance with display contents. After addressing, sustain voltage (also called drive voltage) Vs having alternating polarity is applied to the display electrode pair. The sustain voltage Vs satisfies inequality (1).
VfXYxe2x88x92VwXY less than Vs  less than VfXYxe2x80x83xe2x80x83(1) 
Here, VfXY denotes discharge start voltage between the display electrodes, and VwXY denotes wall voltage between the display electrodes.
When the sustain voltage Vs is applied, cell voltage (sum of drive voltage applied to the electrode and the wall voltage) exceeds the discharge start voltage VfXY only in the cell having a predetermined quantity of the wall charge so that surface discharge is generated on the substrate surface for a display. As an application period is shortened, light emission can be observed as if it is continuous.
A discharge cell of the PDP is basically a binary light emission element. Therefore, a half tone is realized by setting an integral light emission quantity of each discharge cell in a frame period in accordance with a gradation value of input image data. The color display is a type of the gradation display, and a display color is determined by a combination of luminance values of three primary colors. As a gradation display, there is used a method in which a frame is made of plural subframes (subfields for an interlace display) having a luminance weight, and the integral light emission quantity is set by a combination of on and off of the light emission for each subframe. A general driving sequence is as follows. A subframe period that is assigned to each subframe includes a reset period for equalizing charge distribution of the screen, an address period for forming the charge distribution in accordance with display contents, and a display period (or a sustain period) for generating display discharge (or sustain discharge) of the number of times in accordance with the gradation value by applying a pulse train having alternating polarities. Though lengths of the reset period and the address period are constant regardless of the luminance weight, a length of the display period is longer as the luminance weight is larger.
In the conventional driving method, a sustain pulse Ps having a simple rectangular waveform with an amplitude Vs is applied to a display electrode X and a display electrode Y alternately in the display period as shown in FIG. 17. In other words, the display electrode X and the display electrode Y are temporarily biased to potential Vs alternately. Thus, the pulse train having alternating polarities is applied across the display electrode X and the display electrode Y (refereed to as an interelectrode XY). The difference between a pulse base potential (usually the ground level GND) and the bias potential, which is the sustain voltage Vs, is set to a value within a drive margin. The drive margin is defined as a difference between the discharge start voltage Vf and the minimum applied voltage Vsm necessary for sustaining a lighted state. If the sustain voltage Vs is the voltage Vf and above, the discharge is generated also in cells that were not lighted in the addressing period. If the sustain voltage Vs is less than Vsm, a lighted cell becomes a non-lighted state.
Since cells of the PDP are capacitive load for a power source, current flows so as to charge capacitance (CP) of the cell when the sustain pulse Ps is applied. Usually, the display discharge is generated with some delay after the terminal voltage of the capacitance reaches the sustain voltage Vs, while discharge current (referred to as light emission current) flows simultaneously. In the conventional method, the discharge current is supplied to the cell from a power source circuit connected to the PDP. For this reason, a path for supplying the power is long and passes many circuit devices such as switching transistors, so there was a problem of a large power loss and thereby degrading efficiency of the light emission.
An object of the present invention is to reduce the power loss and to increase the efficiency of the light emission.
According to the present invention, capacitance between display electrodes is charged sufficiently for generating display discharge, and after that a current path between a power source and a cell is cut off. Values of charge voltage and charge period are set so that the cut-off timing and the display discharge are overlapped. When display discharge is generated in the cut-off period, the discharge current is supplied to a discharge gap from the charged capacitance. In this case, a path of the discharge current that flows more rapidly than the charge current to the capacitance is located within the cell, so a power loss is smaller than the conventional structure in which the discharge current is supplied from the power source.
FIG. 1 shows a basic drive voltage waveform and a discharge current waveform according to the present invention. The drive voltage waveform is characterized by a step-like waveform including a step for applying voltage Vo higher than sustain voltage Vs to the interelectrode XY, a succeeding step of high impedance and a step for applying the sustain voltage Vs. The high impedance step is a step for cutting off power supply from the power source to the cell. The time for applying the voltage Vo from the leading edge of the waveform is denoted by xe2x80x9cToxe2x80x9d, and the time of the high impedance step is denoted by xe2x80x9cTdxe2x80x9d. In this waveform, a lot of power is supplied to capacitance of the interelectrode XY in the early stages by applying the voltage Vo. After that, when discharge is generated, power is consumed for current flowing in discharge gas. If the external power supply is stopped before the discharge finishes, the power for the current flowing in the discharge gas is supplied from the capacitance of the interelectrode XY. After that, the application voltage is set to an appropriate value of voltage Vs before the discharge finishes, so that the wall charge quantity at the end of the discharge is controlled to be suitable for sustaining.
FIG. 2 is a graph showing dependence of efficiency on the voltage Vo. FIG. 3 is a graph showing drive voltage margin. The light emission efficiency depends on a rate of a part of the discharge current that is supplied from the capacitance. It is desirable to set the voltage Vo such that a peak of the discharge current appears during the period for cutting off the electric path. As shown in FIG. 3, sufficient drive margin can be secured even if the voltage Vo is altered. According to the drive waveform of the present invention, a power loss can be reduced without decreasing the drive margin, so that the light emission efficiency can be improved.